1. Field of the Invention
Embodiments herein present a method, service, computer program product, etc. for performing yield-aware IC routing for a design.
2. Description of the Related Art
Traditional methods for decreasing critical area (and so increasing random-defect yield) in the wiring layers of a VLSI (very large scale integration) layouts control wire spacing, reduce isolated via counts and reduce overall wire length, either during routing or as a post-routing step. Wire spreading (increasing the space between individual wires) reduces the likelihood of spot defects falling between wires and producing shorts; wire-length minimization reduces both the likelihood of spot defects that cause opens and those that cause shorts; and redundant via insertion reduces the likelihood that blocked vias will result in fatal (yield reducing) defects.
Thus, the conventional way to affect random-defect opens is by reducing overall wire length. In a dual-damascene manufacturing process, the incidence of wiring opens is much more significant than in previous technologies. There is a clear need for more effective techniques to reduce the likelihood of opens.